An improved strategy with transistor re-sizing capability for converting bulk CMOS polygon layout to SOI

Abstract

The SOI (Silicon On Insulator) CMOS has many potential advantages over the traditional bulk CMOS circuit as it is free of latch-up and has improved performance and higher packing density. With the recent advances in high-quality thin-film SOI wafer technology, it is becoming a viable technology for ULSI. As SOI emerges as an alternate to bulk CMOS for low power and high-speed applications, an automated methodology will expedite the conversion of existing bulk CMOS designs to SOI CMOS.