A methodology for converting polygon based standard cell from bulk CMOS to SOI

Abstract

The SOI (Silicon On Insulator) CMOS has many potential advantages over the traditional bulk CMOS circuit as it is free of latch-up and has improved performance and a higher packing density. The thin-film fully depleted SOI is the most attractive among other types SOI technologies not only due to its improved property such as subthreshold slope and reduced parasitic, but also due to its simple fabrication process comparing to bulk CMOS. It is becoming a viable technology for ULSI due to recent advances in high-quality thin-film SOI wafer technology. It has same layers as bulk CMOS except the well, the substrate contact and the well contact. In this paper we present a methodology to convert a polygon-based full-custom bulk CMOS to SOI/CMOS. The objective is to convert existing bulk CMOS layout to SOI automatically. The methodology is implemented using the Virtuoso Layout System from Cadence Design System. We shall illustrate the methodology using the Orbit Scalable CMOSN standard cell library.