Abstract
An adaptive decision feedback equalizer (DFE) in 0.18 µm CMOS process for 2.5 GB/s data rate is proposed in this paper which is comprised of three taps. Adaptive DFE circuit is used for the purpose of automatic inter-symbol interference cancellation in cords with different lengths. The status of the high frequency components and low frequency components (LFC) of the signal adjust the coefficient of each tap continuously in online manner. In order to extract the clock, the clock and data recovery circuit is interfused within the DFE. Using the proposed DFE, the status of eye diagram varies from the almost closed to wide open. Total power consumption of the receiver circuit is approximately 50 mW and it occupies the area about 350 µm × 350 µm. Simplicity and less hardware requirements are features of the designed circuit in comparison with the similar circuits.
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