Abstract
A 10 Gb/s adaptive analog decision feedback equalizer (DFE) with 6 taps is realized in 0.13 μm CMOS. A modified Cherry-Hooper stage is designed as the delay element in the feed-forward path. An analog implementation of the LMS algorithm is used to continuously adapt the feedback filter coefficients. A clock and data recovery (CDR) circuit is used to extract the clock from the DFE output. The adaptive DFE dissipates 452 mW and can equalize PRBS data corrupted by a 300m-long multimode fiber (MMF) achieving BER <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-13</sup> .
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