An IGSVL and SGSVL FinFET 6T SRAM-based novel power reduction technique

Abstract

The development of future portable integrated circuits will need to focus on power optimization. As the consequence of continuous current flow, the rise in leakage current in VLSI circuits has recently emerged as a significant issue to solve. It is feasible to reduce the threshold voltage while still decreasing leakage, as long as you don't compromise the other design objectives. An integrated circuit's ability to operate at low power will be more essential in the future. Using current scaling technologies, it seems that Fin FET may potentially be a more practical choice for bulk CMOS. Fin FETs are said to be better than ordinary CMOS transistors since they are double gated. For minimizing power usage, you should use twin gates that are driven simultaneously or independently. In this research, T-Spice is used to install Fin FETs in 45nm SRAM cells that were produced using SRAM cells made in various process technologies to reduce leakage in the circuits under discussion.