An FPGA Charge-to-Digital Converter Based on Voltage-Referenced Receivers for PET Applications

Abstract

A field programmable gate array (FPGA) voltage-referenced standard receiver based charge-to-digital converter (QDC) was proposed. The QDC is based on a linear discharge scheme. In the linear discharge circuit, typically, a low-voltage differential signaling (LVDS) receiver serves as a voltage comparator. Our proposed scheme takes advantage of voltage-referenced standard in the FPGA instead of the LVDS standard, which maximizes the capability of multichannel and multifunctionality. The linearity differences were compared between the voltage-referenced receivers and the LVDS receiver. To validate the scheme for radiation detector application, a 32-channel electronics prototype based on the proposed structure was developed. A positron emission tomography (PET) detector module was built. The detector is made up of a 15 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 15 LYSO array directly coupled with two silicon photomultipliers (SiPM) at two ends. The mean energy resolution for single crystal at the center can reach 17.9%. The linear discharge scheme based on voltage-referenced receivers provides a promising method for a compact, multichannel electronics readout system for radiation detector application.