An FPGA-Based Design of a Fault-Tolerant Shared Memory Structure

Abstract

In this current era of smart computation, faster processing speed is needed. Execution of a process in a parallel manner can achieve higher throughput. For avoiding the Von-Neumann bottle-neck phenomena, the speed of the memories should be high. A high-speed memory can provide contiguous data to a high-speed processor that retains the high performance of that processor. Various high-speed memory technologies are existing in the market such as interleaved memory, cache memory, etc. Multiprocessing technology is also used to achieve high-performance computation. It is still challenging to make a high-speed memory device that can provide data to a multiprocessing system in a contiguous way. Shared memory can fulfill all of the requirements of a multiprocessing system. The efficiency of shared memory can be enhanced by introducing the fault-tolerant mechanism in it without affecting the inter-process communication, which will be discussed in this paper.