An explicit surface potential, capacitance and drain current model for double-gate TFET

Abstract

Abstract In this paper, an explicit analytical model for surface potential, capacitance and drain current is proposed for double-gate tunnel field effect transistor (DG-TFET). For this, n-type doped channel is considered to be working under enhancement-mode where accumulation of charge carriers take place with the applied gate bias. For the first time, a complete physics-based analytical model for terminal charge and capacitance has been developed for the enhancement-mode TFET. For charge and capacitance modeling, accumulated charges and ionized impurity charges are being considered. The model includes the impact of gate bias and drain bias simultaneously. In addition, the model can be scaled down to a channel length of 50 nm. The results obtained from the proposed model agree well with the simulation results of TCAD. Since, an explicit analytical model has been developed without the use of an implicit function, proposed model is SPICE-friendly for circuit simulation.