An error detecting scheme with input offset regulation for enhancing reliability of ultralow-voltage SRAM

Abstract

This paper proposes a new scheme to improve the reliability and reading yield of ultralow-voltage static random access memory (SRAM). The proposed scheme utilizes an error detecting sense amplifier (ED-SA) to constrain SRAM access timing, which combines timing error detection (TED) and correction. ED-SA applies different threshold transistors into the input terminals and regulates input offsets (Voffset) to the different polarity. By this way, the swing of BLs will be enhanced by one of the input offsets and its output will judge the other's correctness. Simulation results in TSMC 28 nm CMOS process design kits show that the proposed scheme has a better significant reading yield improvement compared with conventional error detection techniques.