An efficient VLSI architecture for two-dimensional discrete wavelet transform

Abstract

In this paper, a memory efficient 2-D discrete wavelet transform (DWT) structure is presented for high-speed application. The architecture is based on the modified lifting scheme to reduce the critical path to one multiplier delay. In order to increase the speed of processing, four pipeline stages are introduced in the structure. The computation time for an N × N image is N2/4, as the throughput rate of the structure is four. The results after comparison reveal that the proposed architecture has a temporal memory lower than the other DWT architectures. The Z-scan method is employed to fetch the input data which suits the transpose unit design. Five registers and a multiplexer constitute a transpose unit, which is required to transpose the data between the row and the column processor. The proposed 2-D dual-scan DWT architecture has the merits of low latency, low control complexity and regular signal flow, making it suitable for a very large-scale integration (VLSI) implementation. The architecture is modelled in VHDL and synthesised with the CMOS 180 nm technology.