Efficient FPGA Implementation of 2-D DWT for 9/7 Float Wavelet Filter

Abstract

In this paper, an efficient VLSI architecture which performs the two-dimensional (2-D) 9/7 float discrete wavelet transform (DWT) for the Consultative Committee for Space Data Systems (CCSDS) image data compression is proposed. The 2-D DWT architecture is composed of two one-dimensional processors (row and column processors). The multipliers based on canonic signed-digit (CSD) are used to optimize the design of the 9/7 float wavelet finite impulse response digital filter. This architecture is a pipeline and memory efficient, improving the implementation of the 2D-DWT by adopting an efficient usage of hardware resources, low control complexity; and reducing the embedded memory requirements and external memory access. Based on the line-based architecture, the column processor can start column wise transform while only five rows have been processed. For an 2N × 2N image, only 11 × 2N internal memory is required for the 9/7 float 2-D DWT. Finally, RTL simulation results are presented to show that the proposed architecture is fast and efficient for the 2-D DWT computation.