A Memory Efficient, High Throughput and Fastest 1D/3D VLSI Architecture for Reconfigurable 9/7 & 5/3 DWT Filters

Abstract

In this paper, we have proposed a low area, high throughput parallel VLSI architecture of 3D Discrete Wavelet Transform (DWT). First of all, we have proposed a multiplier-less conventional 1D DWT architecture which has high throughput like 4 outputs / clock cycles. We have greatly reduced the number of Multiply and Accumulation (MAC) units needed for our ID DWT design in comparison to any other conventional DWT architectures. Inside MAC units, all the multipliers are replaced by Shift and Add module to reduce the area. All the adders used in our design are non-conventional speculative adders which have one special feature like highest processing speed. Thus using such adder, the propagation delay time has greatly been reduced. Our proto-type ID DWT architecture is reconfigurable as it can be used to realize the output of both 9/7 and 5/3 DWT filters. By using this ID DWT architecture as both row and column processor, we have designed 3D DWT architecture where we have efficiently reduced the internal buffer size to zero by reusing the off-chip input memory for storing the intermediate data also. By carefully controlling the sequence of operation and maintaining proper timing, we have been able to achieve a high processing speed of $\displaystyle \frac {N^{2}}{4}$ clock cycles/ 2 frames for the overall 3D DWT architecture, where the frame size is (N X N). Throughput of our proposed 3D DWT architecture is also 4 outputs / clock cycles which are exactly same as our proposed ID DWT architecture.