Abstract
This paper proposed an efficient phase-locked loop (PLL) that features zero steady-state error of phase and frequency under voltage sag, phase jump, harmonics, DC offsets and step-and ramp-changed frequency. The PLL includes the sliding Goertzel discrete Fourier transform (SGDFT) filter-based fundamental positive sequence component separator (FPSCS), the synchronousreference-frame PLL (SRF-PLL) and the secondary control path (SCP). In order to obtain an accurate fundamental positive sequence component, SGDFT filter is introduced as it features better filtering ability at the frequencies that are integer times of fundamental frequency. Meanwhile, the second order Lagrange-interpolation method is employed to approximate the actual sampling number including both integer and fractional parts as grid frequency may deviate from the rated value. Moreover, an improved SCP with single-step comparison filtering algorithm is employed as it updates reference angular frequency according to the FPSC, which promises a zero steady-state error of phase and improves the frequency tracking speed. In this paper, the mathematical model of the proposed PLL is constructed, its stability is analyzed. Also, design procedure of the control parameters is presented. The effectiveness of the proposed PLL is confirmed by experimental results and comparison with advanced pre-filtering PLLs.
Highlights
The information about instantaneous grid voltage phase and frequency are usually obtained via phase lock loop (PLL), which is of vital importance to maintain synchronization and stable operation for grid-connected power electronic devices [1,2,3,4,5]
The presence of DC offsets and harmonics in grid voltages caused by measurement devices, nonlinear loads and grid faults throws down a new challenge to the synchronization technique [6]
Considering that adopted to approximate the actual sampling number r, in order to make the sliding Goertzel discrete Fourier transform (SGDFT) filter effective that the practical grid frequency may deviate from therated ratedvalue, value,Lagrange-interpolation the practical grid frequency may deviate from the method is is under variable frequency
Summary
The information about instantaneous grid voltage phase and frequency are usually obtained via phase lock loop (PLL), which is of vital importance to maintain synchronization and stable operation for grid-connected power electronic devices [1,2,3,4,5]. One representative method is the in-loop filtering technique which adds various specific filters in the phase control loop, such as adaptive notch filter-based PLL [10], moving average filter-based PLL (MAF-PLL) [11], Type-1 PLL [12], dq-frame delayed signal cancellation operator based-PLL [13] and the variable sampling period filter based PLL (VSPF-PLL) [14] These PLLs show satisfactory performances but they are not applicable to the situation where precise fundamental positive sequence component (FPSC) is needed. References [24] proposes a generalized delay signal cancelation-based (GDSC) pre-filtering PLL, which can eliminate the negative-sequence component and any given harmonics under unbalanced voltages, harmonics and DC offsets.
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