Abstract
For synchronization applications, synchronous reference frame (SRF) phase-locked loop (PLL) is widely deployed. Its performance is excellent when the input voltage consists of only fundamental positive sequence (FPS) component. If the grid voltage is unbalanced or polluted with harmonics and dc offset, its performance degrades. Many modifications were proposed to address this issue. However, the removal of dc offset and fundamental negative sequence (FNS) component without compromising the dynamic performance still remains a challenging task. To this end, this paper presents a rapid Type-1 SRF PLL scheme with preloop filtering stage for tracking the attributes of grid voltage FPS component. Fixed sampling period sliding discrete Fourier transform (SDFT) and instantaneous symmetrical components method are employed in the preloop stage. With this modification, the dc offset, harmonics and the FNS component are rejected and only the FPS component enters the PLL. As a result, transients vanish quickly. However, when the grid frequency drifts, SDFT causes amplitude and phase errors, and Type-1 PLL introduces a steady-state tracking error in phase. These errors are compensated with the help of an error correction criteria. Robustness and the improved transient response of the proposed scheme are demonstrated with an experimental study involving real-time controller board (dSPACE DS1104) and three-phase programmable power source.
Published Version
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