Design of synchronous reference frame phase‐locked loop with the presence of dc offsets in the input voltage

Abstract

A novel small-signal state-space model is formulated for the commonly used synchronous reference frame phase-locked loop (SRF-PLL). Using this model, the effect of dc offsets as a function of SRF-PLL design parameters is quantified. It is shown that the unit vectors produced by the phase-locked loop (PLL) will have dc offsets when the input contains dc offsets. This can result in dc injection to the grid, which is highly undesirable. A systematic design method is proposed which ensures that dc injection to the grid is within the prescribed grid interconnection standards. In this design, SRF-PLL bandwidth is analytically computed for different levels of dc offsets in the input. The proposed design is compared with conventional pre-filter-based designs addressing the dc offset issue. The proposed design method results in the fastest transient response for given worst-case input dc offset without changing the PLL structure. Such a design for the SRF-PLL is computationally less intensive and is preferable when low-end digital controllers are used. The analytical results have been verified experimentally.