An efficient memory controller for 3D heterogeneous integration platform

Abstract

This paper presents an efficient memory controller VLSI design for integrating a 3D heterogeneous MorPACK system. The MorPACK system is a platform-based integration system and its structure is stacked by heterogeneous sub-modules. In order to reduce fabrication cost and increase the flexibility of memory extension, a novel multimode memory controller is proposed in this paper. The multimode memory controller supports NOR flash, NAND flash, and SDRAM memory with a wide capacity range. Hence, different MorPACK systems for various applications can be integrated by using the same multi-mode memory controller to satisfy different memory requirements. To demonstrate the effectiveness of the proposed methodology, three single-mode memory controllers are also implemented. With the technique of sharing one system-side signals, the pin count can reduce 41.9% while the pin count can reduce 19.2% by applying the technique of sharing memory-side signals. The total silicon area of single-mode memory controllers is about 6.83-mm2 in the TSMC 90 nm CMOS generic logic process technology. Compared with the total chip area 3.1-mm2 of our proposed multi-mode memory controller, the results show that there are 54.7 % fabrication cost reduced.