Abstract
The available flash devices are NAND flash and NOR flash memory devices. Each device is also divided with data width into x8 / x16 NAND flash memory and x8 / x16 NOR flash memory. We are going to implement Flash Controller which is the interface between x8 NAND flash device and the CPU/processor. The same concept will be used for other devices like x8 NOR also. Normal interface is between one x8 NAND flash device and CPU or Processor. This paper proposed a design to interface eight x8 NAND flash devices with CPU/processor. The main feature of the implementation is parallel write operation of eight x8 NAND flash devices. As the numbers of flash devices are 8, it requires dedicated DMA buffers for each x8 NAND flash device. Also to support parallel writes, it is required to read the data of a next DMA write from DRAM while current NAND flash write is in progress. Hence DMA engine is divided into two parts – Flash Side DMA Engine (DMA) and Host Side DMA Engine (HDE). These DMA engines are used to control the above operation.
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