An efficient HW/SW integrated verification methodology for 3D Graphics SoC development

Abstract

This paper proposes an efficient HW/SW integrated verification methodology for 3D Graphics (3DG) acceleration on SoC development. The proposed methodology is built for verifying 3DG SoC with FPGA emulation and contains a GUI analyzing tool for displaying emulation results and assisting HW/SW debugging automatically. With the verification methodology, designers can detect unobvious bugs from HW and SW modules individually and shorten the verification time during SoC integration. In this paper, we will introduce the implemented environment of 3DG SoC and elucidate significance and necessary of proposed method. For the convenience of verification, the analyzing tool that we have developed contains the functions of displaying frame results, comparing different benchmarks, recording FPGA emulation, detecting pixel color, and analyzing bug statistics. As a result, this verification methodology with analyzing tool will help designers to easily verify the complicated 3DG SoC.