An efficient ASIC solution for measurement of telephone dial test parameters

Abstract

A new architecture and innovative logic designs are presented for miniature low-power hand-held telephone dial tester for implementation on a 3 μm CMOS gate array. It is an all digital ASIC hardware containing 2012 two-input equivalent NAND gates and a power dissipation of 150 microwatts at the operating frequency of 2 kHz and 5 V supply voltage.