Abstract

A BiCMOS (bipolar complementary metal-oxide semiconductor) gate array with nearly the same density as a standard CMOS array has been realized using an advanced 1.5- mu m BiCMOS process and a channelless architecture. A two-input BiCMOS NAND gate has a delay of 800 ps when driving a load of sixteen, which is half the delay in CMOS. Arrays with up to 123 K equivalent gates can be achieved with an optimal ratio of CMOS logic gates and BiCMOS blocks. >

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