Abstract

This paper presents an effective encoding technique for super FEC. By using the pre-coding technique, the encoder can process data segmentally and can be multiplexed by multiple data coming from different code words, reducing the storage space of payloads and latency. A concatenated BCH encoder using this improved encoding technique has been designed and realized in FPGA. Simulation results show that the data rate can be up to 10Gbps under the working frequency of 156MHz and the memory usage and processing latency are significantly decreased

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