Mitigating bitline crosstalk noise in DRAM memories

Abstract

DRAM cells in deeply scaled CMOS confront significant challenges to ensure reliable operation. Parasitic capacitances induced by certain bit storage patterns, or bad patterns, create coupling noise that can cause crosstalk-induced faults when the coupling exceeds tolerable margins. These margins decrease and their variabilities increase with scaling, leading to weak cells that are highly susceptible to this form of crosstalk. This paper explores coding techniques to address row-based crosstalk. First, n-to-m bit encoding is explored to remove bad bit patterns from code words. Second, a Periodic Flip Encoding (PFE) technique is proposed to flip specific bits in a repeated pattern with different offsets and produce multiple code word candidates. PFE encoding can be used in a fault-oblivious or fault-aware fashion. Fault-oblivious PFE mitigates faults when the location of weak cells is unknown by minimizing the number of bad patterns in the encoded data. Fault-aware PFE avoids faults when the location of the weak cells is known by selecting the code word in which the center of any bad pattern does not coincide with a weak cell. Fault-aware and fault-oblivious PFE provide two fault tolerance solutions with a trade-off between reliability improvement and performance and power overheads. Experimental evaluation demonstrates that PFE outperforms n-to-m bit encoding as well as other leading approaches, including error correction pointers (ECP) and error correction codes (ECC). For example, when 0.01% of the cells are weak, fault-aware PFE achieves an Uncorrectable Bit Error Rate (UBER) smaller than 3×10−12 compared to 1.4×10−6 for ECP and 6.8×10−6 for ECC-1. When a relatively high 1% of the cells are weak, fault-aware PFE improves the UBER more than two orders of magnitude compared to ECC-1 and one order of magnitude compared to ECP. This is accomplished in both cases with a low performance overhead of between 1--2%, depending on the hardware implementation.