An Area Time-Efficient Structure to Find the Approximate First Two Minima for Min-Sum-Based LDPC Decoders

Abstract

Aiming at reducing the hardware complexity of low-density parity-check (LDPC) decoders based on min-sum algorithms, this brief presents a general structure to find the minimum value and an approximate second minimum value. The proposed structure is proved to obtain the exact second minimum value with high probability in theory, and simulation results demonstrate that only a negligible degradation of error performance is introduced when adopting the proposed structure in LDPC decoders. Furthermore, mixed radix architecture is investigated to improve the area-time efficiency. Implemented in a SMIC 65-nm CMOS technology, the proposed architecture significantly improves the overall area-time efficiency compared with state-of-the-art works.