Abstract
An analytical model for fully depleted SOI MOSFETs is presented. Major small geometry effects such as carrier velocity saturation, mobility degradation, channel length modulation, and drain induced barrier lowering are included. Device self heating due to low thermal conductivity of a buried oxide layer is included in carrier mobility modelling. Thermal effects are also included in threshold voltage expression. Source, drain, and channel resistance effects are also included. Modelled results are then compared to available measured data and are shown to be in very good agreement.
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