An analytic model of holding voltage for latch-up in epitaxial CMOS

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For epitaxial CMOS in the latched state, the region between the anode and the cathode is conductivity modulated. In this case, the two-transistor model for the silicon-controlled rectifier (SCR) is not valid. However, a simplified analysis is possible because the well-substrate junction is obliterated by carriers. With this approach an analytic model is developed which can predict the holding voltage and its dependence on design parameters. The model is capable of predicting quantitatively the improvement in holding voltage with increased n+ -to-p+ spacing, thinner epi, substrate backbias, shallow trench, and silicided junctions and higher epi doping. The model explains a previously observed scaling law for the holding voltage.