Abstract
Conventional floating gate flash memory has been the mainstream VLSI memory for the past decade. However, as the gate length scaled into nanoscale regime, it is great challenge to continue the scaling pace due to the physical limit of the tunneling oxide and its related reliability issues. Alternatively, the SONOS (silicon-oxide-nitride-oxide-silicon) cell structure offers a promising solution to further scale as code and data flash memory. A compact, analytic model of the threshold voltage variations in SONOS memory was derived to describe the impact of lateral migration on devices characteristics by using gate voltage equation. Since no empirical fitting parameters are involved in this model, it is very helpful in cell design and the prediction of scaling limit for next generation applications.
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