Abstract
This paper describes the VLSI realisation of a novel neural network implementation architecture which is geared to the processing of frame based data. The chief advantage of this architecture is its elimination of the need to implement total connectivity between neural units as hard-wired connections. This is achieved without sacrificing performance or functionality. A detailed description of the implementation of this architecture in 2μ CMOS, using a mixed analogue and digital building blocks is given together with details of system level design.
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