Abstract
A cellular analog processor array for use in variable block-size motion estimation with a new simple method for shifting reference image data is presented. The new shift method leads to a greatly reduced number of neighborhood connections for each cell of the array, and allows for all shifts within the [8,8] search area to be performed in a single step, with simple digital controls. The new shift circuitry, together with some other cell and system level optimizations, reduces silicon area and array layout complexity, enabling faster and more efficient parallel full search motion estimation hardware. A 32 × 32 cell parallel analog test array for reference-shift with a maximum block-size of 16 × 16, as well as absolute value/quadratic processing for variable block-size analog motion estimation (AME) has been designed in a 0.13 µm CMOS technology.
Highlights
Cameras withmegapixel sensors have become ubiquitous in even relatively low-end mobile phones
This paper describes the implementation of parallel processing hardware for an analog motion estimation (AME) array, with a focus on the implementation of a new reference data shift method
Because current-output DACs and current-mode processing are used, the output current of a DAC can be redirected through a switch either to the local difference block or to the shift network. This way only the reference frame data has to be written into the cells in each motion estimation step, and power and time is saved during the read-in phase of the processor array
Summary
Cameras with (multi-)megapixel sensors have become ubiquitous in even relatively low-end mobile phones While this makes good quality still imaging possible, the limited amount of memory and processing power in such a batterypowered mobile platform often prohibits the use of the best available image quality for capturing video streams; typically a considerably poorer video capture resolution is used. This paper describes the implementation of parallel processing hardware for an analog motion estimation (AME) array, with a focus on the implementation of a new reference data shift method. This paper extends the original paper proposing the new reference-shift method [9], by describing in detail the implementation of other circuitry for the array cell as well as presenting the implementation of a 32×32 cell AME test chip that has been designed and submitted for manufacturing.
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