Abstract

Increase in the complexity of VLSI digital circuit design demands faster logic simulation techniques than those currently available. One of the ways of speeding up existing logic Simulation Agorithms is by exploiting the inherent parallelism of the sequential version. In this paper, we explore the possibility of mapping an event driven logic simulation algorithm onto a cluster of processors interconnected by an ethernet. The set of events at any simulation time. step is partitionecl by the Master Task (running on the host processor) anlong the Worker Tasks(running of the other processor's). The partitioning scheme ensures a balanced load. Each Worker Task determines the fanout, elementts, evaluates them independently and comes up with the new event list which is passed onto the Master Task. After receiving the event lists from all the workers, the Master Task increments the simulation time step, computes the new event list partition for the next simulation cycle. We have implemented this distributed logic simulation algorithm on a set of 8 VAXstations using CT - a package for distributed programming. The paper concludes with a note on the speedup figures obtained on the ISCAS benchmark circuits.

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