An 8-b 250-Msample/s power optimized pipelined A/D converter in 0.18-µm CMOS

Abstract

The optimal pipeline analog to digital converter (ADC) architectures are analysed to determine the optimal partitioning and particular bits per stage for power optimization purpose. It is found in our design that the multi bit partitioning with 2.5 bits per stage resolution, is optimum in terms of power consumption compare to the 1.5 bits per stage for an 8-bit pipeline ADCs circuit. The optimal partitioning of the 8-bit ADC is realized with 2.5-2.5-2.5-2 cascading stages and another topology with 1.5-1.5-1.5-1.5-1.5-1.5-2 cascading stages employed with double sampling sample hold (DSSH) architecture. ADCs are implemented in 0.18 µm CMOS and 8-bit with 2.5 bits/stage resolution ADCs achieved 43 dB SINAD, 50.78 dB spurious free dynamic range (SFDR) for an input signal frequency of 1.7 MHz at 250 MSPS, and power consumption is 27 mW from a 1.8 V power supply. An 8-bit 1.5 bits/stage resolution ADC with the same technology process achieved 47.20 dB SINAD, 60.6 dB SFDR for an input signal frequency of 1.7 MHz at 250 MSPS, and power consumption is 49 mW from a 1.8 V power supply.