An 8-bit 100-MS/s pipelined ADC without dedicated sample-and-hold amplifier

Abstract

An 8-b 100-MS/s pipelined analog-to-digital converter (ADC) is presented. Without the dedicated sample-and-hold amplifier (SHA), it achieves figure-of-merit and area 21% and 12% less than the conventional ADC with the dedicated SHA, respectively. The closed-loop bandwidth of op amps in multiplying DAC is modeled, providing guidelines for power optimization. The theory is well supported by transistor level simulations. A 0.18-μm 1P6M CMOS process was used to integrate the ADCs, and the measured results show that the effective number of bits is 7.43 bit and 6.94 bit for 1-MHz and 80-MHz input signal, respectively, at 100 MS/s. The power dissipation is 23.4 mW including voltage/current reference at 1.8-V supply, and FoM is 0.85 pJ/step. The ADC core area is 0.53 mm2. INL is −0.99 to 0.76 LSB, and DNL is −0.49 to 0.56 LSB.