An 11-b 300-MS/s Double-Sampling Pipelined ADC With On-Chip Digital Calibration for Memory Effects

Abstract

An 11-b 300-MS/s double sampling pipelined ADC with on-chip digital calibration for memory effects is presented. In double-sampling pipelined ADC architecture, memory effect of residual charge occurs due to sharing an op-amp between two channels of pipelined ADC. The proposed foreground calibration technique removes the memory effect error in digital domain without additional analog circuit. Thus, the technique simplifies the analog circuits, which extends the operation speed over 300 MHz. The chip is fabricated in a 40 nm CMOS and occupies 0.42 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> including digital calibration logic. The ADC consumes 40 mW from a 1.8 V supply, and FoM is 0.24-pJ/conversion-step.