Abstract
ABSTRACTAn alternative approach for reduction of interface traps density at 4H-SiC/SiO2 interface is proposed. Silicon nitride / silicon oxide stack was deposited on p-type 4H-SiC (0001) epilayers and subsequently over-oxidized. The electrical characterization of the interface was done by employing metal-oxide semiconductor (MOS) devices, inversion-channel MOS devices and lateral MOS field effect transistors (MOSFETs).
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
