ALFANS: Multilevel Approximate Logic Synthesis Framework by Approximate Node Simplification

Abstract

Approximate computing is an emerging design paradigm targeting at error-tolerant applications. It trades off accuracy for improvement in hardware cost and energy efficiency. In this paper, we propose ALFANS, a novel multilevel approximate logic synthesis framework by approximate node simplification. ALFANS works on the Boolean network representation of circuits. Its basic operation is to perform approximate simplification to nodes in a Boolean network. Based on this framework, we propose three different algorithms for three different types of error constraints. The first algorithm, ALFANS-ER, handles error rate (ER) constraint only. The second one, ALFANS-ER-MEM, handles a combination of ER and maximum error magnitude (EM) constraint. The third one, ALFANS-ER-AEM, handles a combination of ER and average EM constraint. All these three algorithms repeatedly pick the single most effective node to simplify in each iteration. When only the ER is constrained, we also propose an accelerated version, ALFANS-ER-Fast, which formulates a knapsack problem to pick multiple nodes for simplification simultaneously in each iteration. It significantly improves the runtime over ALFANS-ER with almost the same circuit area. Compared to the respective state-of-the-art approaches handling the same type of error constraint, ALFANS-ER-Fast and ALFANS-ER-MEM reduce circuit area by 1.3% and 19.5%, respectively. A salient feature of ALFANS-ER-Fast is its run-time efficiency: it has a speedup of $5.9 \times $ over the state-of-the-art method.