AI SoC-Based Accelerator for Speech Classification Accélérateur de classification de la parole basé sur un AI SoC

Abstract

Speech classification acceleration using field-programmable gate arrays (FPGAs) is a well-studied field and enables the potential to gain both speed and better energy efficiency over other processor-intensive classifiers. System-on-chip (SoC) architecture allows for an integrated system between programmable logic and processor and for increased bandwidth communications to on-chip peripherals and memory. This article serves as an investigation of the utility of an edge-based support-vector machine (SVM) implemented onto a Zynq-XC7Z020 multiprocessor system on a chip (MPSoC) for the acceleration of three speech class pairs. The system allows for a parallelized structure, which yielded a faster classifier model. The results were found to be an acceleration factor of 2.08 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> . This appears to have come at the cost of a decrease in prediction accuracy, lowering from 92.5% to 83.5% positive prediction percentage likely due to decreased data resolution. The resolution used in this model was a 16-bit fixed-point format for the hardware interpretation and a floating-point format for the software benchmark. The resource usage of the FPGA was also analyzed for both overlays and can yield a 21% reduction in CPU usage.