Aging mitigation of L1 cache by exchanging instruction and data caches

Abstract

By shrinking the transistors' dimensions, some aging phenomena effects that were negligible in previous technologies have become the most serious reliability threats. The most important aging process is Bias Temperature Instability (BTI). This phenomenon dissociates the chemical bonds between the silica lattice and hydrogen at the interface between the gate insulator and the transistor channel. The SRAM structures are vulnerable to BTI due to the long stress time on the transistors of this structure during normal system operations. Regardless of the stored values on the SRAM cells, the cross-coupled structure of this cell leads to continuous stress on at least two transistors of the cell at a given time. To mitigate the aging of the SRAM structures, like cache memories, there are many aging avoidance and aging mitigation techniques in the literature on this topic. However, the overheads or the efficiency thereof are not tolerable in many cases. This paper proposes an aging mitigation mechanism for cache memories by exchanging the values that are periodically stored in data and instruction caches. The results show that while the area and performance overheads of the proposed mechanism are negligible (less than 1%), the average stress time on the cache memories decreases by 2.39×, which prolongs the Mean Time to Failure (MTTF) of the memory structure by 1.91×.