Multi-level cache vulnerability estimation: The first step to protect memory

Abstract

Cache is one of the most susceptible microarchitectural components against soft errors since cache memory not only takes up the majority of chip area but also is frequently accessed by other microarchitectural components. Several protection techniques have been proposed in order to improve the cache reliability. These cache protections can significantly affect the overall performance of the entire processor. Thus, it is extremely important to quantify the reliability of cache memory with and without protections in order to choose appropriate protection techniques. In this paper, we model the vulnerability estimation with considering generally used protection techniques, such as parity and error correction code, on multi-level cache memory. In common processors, level 1 and 2 caches are protected by parity and error correction code, respectively, but our experimental results reveal several interesting results. First off, parity protection for level 1 instruction cache can be good way to decrease the vulnerability, but it is inefficient for level 1 data cache. In special cases, parity protection for level 1 data cache can worsen the reliability as compared to unprotected cache. Secondly, parity protection for level 2 cache can decrease the vulnerability almost by half with the comparable overheads. For some benchmarks, parity protection for level 2 cache can be as reliable as error correcting code with much less overheads.