Abstract
Smart phone and tablet devices are making our lives more convenient, informative, and enjoyable. Underpinning the development of these devices are semiconductor package technologies, which are being pushed to the limit. The Controlled Collapse Chip Connection (C4) process had been the major packaging technology for flip chip devices, which provides more I/Os and faster communication speeds. However, lower silicon node, fine pitch bumping and wafer thinning make the silicon chip more fragile. The delicate nature of modern silicon chips are making stress management and structure protection major topics for advanced semiconductor package and process design. Henkel provides a wide range of underfill materials that address the challenges of new electronic package designs. Non-conductive paste (NCP) products with thermal compression bonding (TCB) process enable the use of fine pitch copper pillar bumping with lower silicon node dies. New capillary underfill (CUF) development offers lower warpage while maintaining high Tg and modulus. Wafer applied underfill film (WAUF) has also been developed and is a key technology for emerging 2.5D and 3D IC packages.
Published Version
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