Process integration of solder bumps and Cu pillar microbumps on 2.5D fine pitch TSV interposer

Abstract

The use of portable electronic devices like smart phones and tablets results in high demand for more function, smaller dimensions and reduced power consumption requirements. To meet these challenges, electronic package design uses thinner chips with fine pitch bumping. There has been active development in 2.5D and 3D IC packages with through silicon via (TSV). Tighter interconnection in addition to the increased density in the circuit in 2.5D and 3D IC systems provide higher performance with lower power consumption [1]. In addition, the down scaling trend of CMOS technology beyond 28nm node requires smaller chip size for a given input/output (I/O) count, pushing the interconnect pitch smaller and smaller. When the bump pitch is less than 50μm and the gap between the die and substrate is lesser than 25μm, traditional capillary underfill (CUF) material is likely to require a vacuum or pressure assisted process to pull the underfill and fill the gaps without any voids [2]. The narrower gap also makes flux cleaning after reflow more challenging. The development of wafer-level underfills can bring the financial benefits of wafer-level processing to flip chip assembly and packaging. The flip chip assembly is the application of underfill at the wafer level, eliminating the dispense, flow, and separate cure steps associated with assemblies utilizing capillary-flow underfills. In addition, the wafer-level material should include fluxing capabilities similar to no-flow underfills [3]. In this paper we describe the assembly process and challenges of the 100μm thin 2.5D TSV Si interposer to the test substrate and the assembly of three different test chips onto TSV Si interposer using capillary underfill and WL-UF (NST series from Nissan Chemical Industries, Ltd). The TSV Si interposer provides high density multilevel routing on the frontside of the wafers and through-silicon vias (TSVs) to connect the frontside metallization with the backside metallization for connection to the PCB [4].