Advanced high-k/metal gate stack progress and challenges – a materials and process integration perspective

Abstract

Abstract Scaling of complementary metal oxide semiconductor devices is critical to enhancing performance and reducing the production cost of transistors. Conventional gate stack film systems consisting of a SiO2 dielectric layer between the Si substrate channel and a doped polycrystalline silicon (poly-Si) gate electrode exhibited excessively high gate current leakage when the physical thickness of this traditional dielectric was scaled to Tphys = ∼2 nm. The rate of scaling was initially preserved by incorporating nitrogen to form an SiOxNy insulator layer; however, this material soon experienced unacceptable levels of direct tunneling leakage current, which launched an industry-wide investigation of potential high dielectric constant (high-k) metal oxides as replacement materials for the SiO2 based gate dielectric layer. Thermal stability requirements for the introduction of high-k dielectric materials necessitated the simultaneous replacement of poly-Si with a metal gate electrode due to several performance factors including unscalable threshold voltage. Although high-k/metal gate thermal stability has been demonstrated, significant challenges remain to be resolved for future technology nodes. This paper reviews the progress and challenges associated with the introduction of high-k/metal gate transistors, including threshold voltage tuning and gate dielectric thickness scaling, from a materials and process integration perspective.