Adaptive sized Quasi-Monte Carlo based yield aware analog circuit optimization tool

Abstract

This paper proposes an efficient Quasi-Monte Carlo based yield aware analog circuit synthesis tool with an adaptive sampling mechanism. Monte Carlo (MC) analysis is commonly preferred to estimate process variation effects on the yield of manufactured ICs. However, conventional MC requires a large number of simulations for accurate estimation. This situation causes excessive synthesis times during yield aware optimization, where many iterative variability simulations are performed. To enhance the efficiency, Infeasible Solution Elimination approach is utilized, in which yield estimation is not performed for infeasible solutions. In addition to this approach, a more efficient MC method, called Quasi-Monte Carlo (QMC), is used to generate samples from the uncertain parameter space. Thanks to the homogeneous distribution of samples, the required number of simulations is substantially reduced. Furthermore, QMC allows iterative generation of samples; hence enabling the sample size to be increased without restarting the entire simulation from the beginning. Using this property of QMC, an adaptive mechanism is proposed to determine the minimum sample size required for accurate yield estimation. The yield term is introduced as a new design constraint to the optimizer together with the electrical constraints. Finally, the developed tool offers an additional part, where a simulation budget allocation algorithm promises a more accurate yield estimation for the valuable candidates.