Accumulation-Mode Silicon Carbide Laterally Diffused Metal Oxide Semiconductor with Low Specific on Resistance

Abstract

To deal with the conflict of specific on resistance (RON-sp) and breakdown voltage (BV) in design of SiC LDMOS power devices, a SiC LDMOS power device with low RON-sp is given and its principle is studied in the paper. The proposed structure consists of a conduction cell with several poly plates and a modulation cell with floating electrodes. The modulation cell consists of two opposite diodes in series and does not participate in current conduction. In the on state, gate voltage (VG) is delivered to modulation cell, which is held on by P+/N-well junction in drain side. Then the floating electrodes deliver VG back to the conduction cell for electron attraction. Because a electron accumulation layer is existed on surface of N-drift region, a low resistive current path is formed. The low resistive current path greatly decreases RON-sp of SiC LDMOS. In the off state, modulation cell can be designed to reach a high BV without considering the forward conduction performance. In the conduction cell, thanks to the potential modulation of poly plates connected to floating electrodes, a high BV can also be obtained. Experimental results and comparison analysis show the given SiC LDMOS gains better performance than traditional SiC LDMOS. RON-sp is 34.8% less than traditional SiC LDMOS device without degenerating BV.