Accumulation-mode high voltage SOI LDMOS with ultralow specific on-resistance

Abstract

A high breakdown voltage (BV) thin SOI LDMOS with ultralow specific on-resistance is proposed and its mechanism is investigated. The LDMOS features an accumulation-mode extended gate (AEG) structure on the surface that consists of a P- region and two diodes in series. In the on-state, an electron accumulation layer is formed at the drift region surface and provides an ultralow resistance current path, which dramatically decreases the specific on-resistance (R on-sp ) and obtains a very low and even-distributed temperature. In the off-state, the P- region in AEG depletes the N-drift region, and hence increases the drift doping concentration (N d ) and further decreases the R on-sp . Moreover, the two reverse biased diodes sustain the gate to drain voltage in the on-state and offstate respectively, ensuring a high breakdown voltage and low leakage current. Compared with a conventional thin SOI LDMOS, the proposed device reduces the R on-sp by 70% and increases the BV by 7%.