Abstract
Several novel methods for the electrical-level simulation of digital VLSI MOS circuits on a shared-memory multiprocessor system are presented. A novel parallel algorithm, the overlapped phases algorithm, for the efficient simulation of circuits containing feedback loops, is presented. The algorithm is based on data flow scheduling and local relaxation of the feedback loops. A novel method for the partitioning of largepass transistor networks is discussed. The method is based on the signal flow direction in the elements. This partitioning allows an efficient simulation of these large networks on a multiprocessor system. Parallel element evaluation and the time segment pipelining method, two methods to increase the performance of the parallel circuit simulator, are explained. Simulation tests with actual circuits show a substantial acceleration for the new methods. >
Published Version
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