Accelerated reverse emitter-base bias stress methodologies and time-to-failure application

Abstract

A second current-acceleration method for measuring the reliability of silicon bipolar transistors under reverse emitter-base bias stress is demonstrated in this paper. The low-voltage operation condition in submicron transistors may be attained during the stress experiments, providing an accurate determination of the transistor's operation time-to-failure (TTF) without extrapolating from higher voltage stress data. Two different current-acceleration stress methods are demonstrated in one transistor design and compared with the traditional voltage-acceleration method using the carrier kinetic energy as the independent variable. It is shown that the traditional voltage-acceleration method can give an erroneous and larger extrapolated time-to-failure by several orders of magnitude in some devices.