Analysis and Modeling for Reverse Body Bias Stress Impact on HCI Induced Degradation in n-Type EDMOS

Abstract

Reverse body bias (RBB) stress impact on high-voltage (HV) n-Type extended-drain MOSFET (EDMOS) has been investigated in this paper. Two-step degradation behavior of sub-threshold voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> ) has been observed. At RBB stress lower than -1.25V, there is minor impact of RBB stress on hot carrier induced V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> shift. However, when the stress reaches around -2.5V, the V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> degradation increases significantly and has strong correlation with the RBB stress. Technology computer-aided design (TCAD) simulation shows that the Body/Source junction is reverse biased under large RBB stress therefore band to band tunneling current is generated at the interface near source side. High electric field enhances hot-electron trapping towards gate oxide in the channel region, resulting in large V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> shift after stressing. An equivalent reliability model has been developed based on this phenomenon, and the improved model fits well with the silicon data.