A VLSI architecture for pipeline fft processor

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AbstractThis paper considers the fast‐Fourier transform (FFT) which processes a large amount of data, such as image. As a structure for the one‐dimensional FFT processor, aiming at eliminating some restrictions in VLSI design, the constant‐geometry type FFT algorithm and the bit‐serial pipeline floating‐point arithmetic are discussed. The major results are as follows. (1) Using the constant‐geometry algorithm, the memory elements to perform the rearrangement characteristic to FFT can be realized by a uniform structure and uniform control scheme throughout the stages. The memory element for N‐point FFT can be constructed as a simple and regular structure using 2 of N/2‐stage shift‐registers. (2) The multiplication cell with code extender, the serial structure of normalization circuit and the shifter, and the parallel operation covering a longer length than the input word length are employed. By those schemes, the pipeline operation of floatingpoint arithmetic is realized without a guard bit. By this scheme, the restriction in VLSI using the butterfly elements can be reduced drastically. (3) As an additional effect of the regular structure of the memory element, the automatic defecttolerant operation is made possible, using the effective k‐out‐of‐n redundant structure and the self‐testing. By this scheme, the restriction for the VLSI chip‐area can be reduced when the number of sampling points is increased. (4) The one‐dimensional FFT processor can be realized as a modular structure, which is a cascade connection of two kinds of VLSI, i. e., butterfly element and the memory elements.