A TSV Constrained Algorithm for Designing Balanced Wrapper Chains in 3D SoC

Abstract

AbstractThree-dimensional integrated circuit (3D-IC) has emerged as a saviour of failing Moore’s law, where the reduced length of interconnects is guaranteed with some added advantages like heterogeneous integration, higher computation per volume, etc. These benefits are also exhibited in 3D SoCs (3D System on Chips) to use the already built cores. However, testing these large complex SoCs in lesser time has become a challenge. In this paper, we propose a simulated annealing based wrapper chain design algorithm that will balance the length of the wrapper chain. The number of TSVs (Through Silicon Vias) are also kept as a constraint so that the number of TSVs could also be reduced. Rigorous experiments were being conducted on several ITC’02 SoC benchmarks and the results when compared with a recent work showed that our proposed approach recorded better test lengths in more than \(90\%\) cases with an average reduction of \(9.65\%\) in test length. Our algorithms also used less number of TSVs in approximately \(85\%\) of the cases with an average reduction of \(17.94\%\) in number of TSVs, in comparable CPU time.Keywords3D SoCWrapper designTAMTSVEntropy