Co-Optimization of Test Wrapper Length and TSV for TSV Based 3D SOCs

Abstract

In 3D IC, wrapper chains can span across vertical directions which causes the increase in number of TSVs(through-silicon-vias)(which is used to interconnect different cores in the vertical directions). Excessive use of TSVs in wrapper design causes routing congestion and additional overhead in manufacturing. Therefore, optimization of wrapper length and judicious use of TSVs are the focus of 3D wrapper architecture design. In this work, we first propose a heuristic procedure to determine the placement of wrapper elements in several layers of 3D SOC for a number of wrapper chains and interconnect them using available number of TSVs such that the length of the longest wrapper length (LWL) is minimized. Then we apply particle swarm optimization (PSO) based metaheuristic approach on the results obtained in first case to determine the placement of wrapper chains and interconnect them using minimum number of TSVs such that the length of LWL is minimized. We compare our results with earlier works and the experimental results show the efficacy of our algorithm.