A Transistor Level Link for VHDL Simulation of VLSI Circuits

Abstract

This paper presents programs and models for interfacing VLSI design tools and the VHDL hardware description language. The programs convert CIF files to VHDL component instantiation lists, and extract timing parameters from Spice transistor specifications. The models are simulatable VHDL descriptions for the instantiated components. We will describe various linking alternatives and the details of a switch level linkage. This technique will be useful in an academic setting for integrating VHDL into Magic tool-set.